There has been a growing demand for small low-cost radio communication equipment. To meet this demand, a direct conversion receiver circuit is advantageous because the high-frequency circuit portion is simple, and the number of components can be decreased. However, the direct conversion receiver circuit also has some disadvantages, and one of the major disadvantages is a DC offset voltage.
The DC offset voltage is amplified as the gain of a baseband circuit is increased. Therefore, when the gain of the baseband circuit is the maximum (e.g., 60 dB), the DC offset voltage becomes larger than the power supply voltage of the baseband circuit. Consequently, no signal is transmitted to the output of the baseband circuit.
The DC offset voltage in a conventional direct conversion receiver circuit has been addressed, e.g., by JP 2003-224489 A. FIG. 20 shows a circuit as disclosed in JP 2003-224489 A. The circuit of FIG. 20 is a baseband circuit of a direct conversion receiver.
In FIG. 20, reference numeral 201 denotes a low-pass filter, 202, 204, and 206 denote gain control amplifiers, and 203, 205, and 207 denote high-pass filters. A gain distribution circuit 208 controls the gains of the gain control amplifiers 202, 204, and 206. A control circuit 209 controls changes in the low cutoff frequencies of the high-pass filters, 203, 205, and 207. Anode 2a is the input of the baseband circuit, and a node 2b is the output of the baseband circuit. A node 2c is the input of the gain control amplifier 206, and a node 2d is the output of the gain control amplifier 206. A node 2e is for inputting a gain control signal. A control signal line 2f is for controlling the gain of the gain control amplifier 206. A control line 2g is for controlling the low cutoff frequencies of the high-pass filters 203, 205, and 207.
In this configuration, the DC offset voltage output from each of the gain control amplifiers 202, 204, and 206 is amplified with increasing the gains of the gain control amplifiers. However, due to the presence of the high-pass filters 203, 205, and 207, the DC offset voltage is not transmitted to the outputs of the high-pass filters, so that a DC offset does not occur in the node 2b, which is the final output.
According to the configuration of FIG. 20, a signal can be transmitted to the node 2b (final output) even at the maximum gain of the baseband circuit.
On the other hand, in the case of a direct conversion system, the input signal of the baseband circuit is a baseband signal and also includes a DC as a frequency component. Therefore, the low cutoff frequencies of the high-pass filters 203, 205, and 207 should be as small as possible. However, if the low cutoff frequencies of the high-pass filters 203, 205, and 207 are sufficiently small, a transient response occurs in the outputs of the high-pass filters 203, 205, and 207 when the DC offset voltage output from each of the gain control amplifiers 202, 204, and 206 is changed by switching the gains. The convergence time of the transient response is determined by the time constants of the high-pass filters and thus becomes longer.
When the gains are increased significantly, the transient response in the output of the high-pass filter 205 is amplified by, e.g., the gain control amplifier 206. Therefore, a large transient response occurs in the output of the baseband circuit for a long time.
The circuit of FIG. 20 has a configuration to solve the problem of this transient response. That is, the low cutoff frequencies of the high-pass filters 203, 205, and 207 are varied with changes in the gains of the gain control amplifiers 202, 204, and 206. Specifically, when the amount of change in gain is small enough (e.g., less than 6 dB), the low cutoff frequencies are made as small as possible. When the amount of change in gain is more than a predetermined value (e.g., not less than 6 dB), the low cutoff frequencies are made higher. Thus, even if the gains are increased significantly, the transient response caused by a DC offset can converge quickly.
The above function of the conventional circuit may be useful in the absence of a baseband signal. However, when the gains are increased significantly while the baseband signal is input to the circuit, a transient response occurs due to DC offset voltage fluctuations resulting from the presence of the baseband signal. In addition, the convergence time is longer because it is determined by the time constants of the high-pass filters 203, 205, and 207.
FIG. 21 shows a transient response that occurs when the low cutoff frequencies of the high-pass filters 203, 205, and 207 are varied, e.g., with a significant increase in the gain of the gain control amplifier 206 while the baseband signal is input to the circuit of FIG. 20.
In FIG. 21, (a) indicates a waveform at the control signal line 2f for controlling the gain of the gain control amplifier 206, (b) indicates a waveform at the control line 2g for controlling the low cutoff frequencies of the high-pass filters 203, 205, and 207, (c) indicates a waveform at the node 2c as the input of the gain control amplifier 206, (d) indicates a waveform at the node 2d as the output of the gain control amplifier 206, and (e) indicates a waveform at the node 2b as the final output of the circuit.
The operation of the circuit of FIG. 20 will be described by referring to FIG. 21. As shown in FIGS. 21(a) and (b), the gain of the gain control amplifier 206 and the low cutoff frequencies of the high-pass filters 203, 205, and 207 are switched at time t1. In FIG. 21(b), the low cutoff frequencies of the high-pass filters are changed from high to low at time t2.
Under this control, there is no change in either the signal amplitude or DC voltage in the input node 2c of the gain control amplifier 206, as shown in FIG. 21(c). In the output node 2d, however, the signal amplitude is increased and the DC offset voltage is changed at t1, as shown in FIG. 21(d). After t1, the signal amplitude and the DC offset voltage are unchanged.
Next, the waveform at the node 2b (final output) of the circuit of FIG. 20 will be described by referring to FIG. 21(e). At t1, the gain of the gain control amplifier 206 is increased, and the low cutoff frequency of the high-pass filter 207 is changed from low to high. Then, the low cutoff frequency of the high-pass filter 207 is changed from high to low at t2. Therefore, a signal is interrupted between t1 and t2, and only a DC is output to the node 2b. At t2, the high-pass filter 207 transmits a signal because the low cutoff frequency is changed from high to low, and the signal is output to the node 2b. 
Depending on the phase of the input signal of the high-pass filter 207, i.e., the phase of the signal of the node 2d, DC offset fluctuations whose maximum is half the magnitude of the signal amplitude may occur in the node 2d at t2. The DC offset fluctuations reach the maximum when the input signal of the high-pass filter 207 (the signal of the node 2d) is at its bottom or peak at t2. FIG. 21(e) shows a transient response when the signal of the node 2d is at the bottom.
In a communication mode that performs continuous reception such as W-CDMA, it is necessary to change the gains while signals are being received. Therefore, when the conventional circuit is used for this communication mode, the gains have to be switched during the reception of signals, so that a transient response occurs due to DC voltage fluctuations.